美国专利US20010008301A1 Semiconductor device

专利PDF首页>>美国专利

专利附录

专利说明

权利要求

类似技术

同族专利

引用文献

法律状态

优先权

专利摘要:
A semiconductor device according to the invention of the present application comprises a substrate having a surface on which interconnections are formed, a semiconductor element connected to the interconnections and mounted on the substrate, and a conductive map for covering the semiconductor element electrically connected to a ground potential. Owing to the provision of the conductive cap for covering the semiconductor element in this way, the semiconductor device can prevent the emission of an electromagnetic wave to the outside and can be prevented from malfunctioning due to an external electromagnetic wave.
公开号:US20010008301A1
申请号:US09/777,676
申请日:2001-02-07
公开日:2001-07-19
发明作者:Makoto Terui
申请人:Makoto Terui；
IPC主号:H01L23-49811

专利说明:
[0001] 1. Field of the Invention [0001]
[0002] This invention relates to a semiconductor device, and particularly to a structure of a small-sized area array package. [0002]
[0003] 2. Description of the Related Art [0003]
[0004] A conventional general small-sized area array package has a structure wherein a semiconductor chip is mounted on a substrate composed of an organic material or a substrate composed of a ceramic material, having wires or interconnections formed by a metal material such as copper foil or tungsten or the like with bumps [0004] 2 such as solder, gold or the like interposed therebetween, and external terminals such as solder balls or the like are provided at the lower surface of the substrate in lattice form after a liquid epoxy resin has been charged into an interval or space between the semiconductor chip and the substrate. SUMMARY OF THE INVENTION
[0005] With the foregoing in view, it is therefore an object of the present invention to provide a semiconductor device capable of preventing the radiation of an electromagnetic wave to the outside and a malfunction developed due to an electromagnetic wave sent from the outside. [0005]
[0006] According to one aspect of this invention, for achieving the above object, there is provided a semiconductor device comprising a substrate having a surface with interconnections formed thereon, a semiconductor element electrically connected to the interconnections and mounted on the substrate, and a conductive cap for covering the semiconductor element electrically connected to a ground potential. [0006]
[0007] Typical ones of various inventions of the present application have been shown in brief. However, the various inventions of the present application and specific configurations of these inventions will be understood from the following description. [0007] BRIEF DESCRIPTION OF THE DRAWINGS
[0008] While the specification concludes with claims particularly pointing out and distinctly claiming the subject matter which is regarded as the invention, it is believed that the invention, the objects, features and advantages thereof will be better understood from the following description taken in connection with the accompanying drawings in which: [0008]
[0009] FIG. 1 is a cross-sectional view of a semiconductor device showing a first embodiment of the present invention; [0009]
[0010] FIG. 2 is a plan view of the semiconductor device shown in FIG. 1; [0010]
[0011] FIG. 3 is a partly enlarged view of the semiconductor device shown in FIG. 1; [0011]
[0012] FIG. 4 is a cross-sectional view of a semiconductor device illustrating a second embodiment of the present invention; [0012]
[0013] FIG. 5 is a cross-sectional view of a semiconductor device depicting a third embodiment of the present invention; [0013]
[0014] FIG. 6 is a plan view of the semiconductor device shown in FIG. 5; and [0014]
[0015] FIG. 7 is a plan view of the semiconductor device shown in FIG. 5. [0015] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
[0016] Preferred embodiments of the present invention will hereinafter be described in detail with reference to FIGS. 1 and 2. [0016]
[0017] FIG. 1 is a cross-sectional view of a small-sized area array package showing a first embodiment of the present invention. FIG. 2([0017] a) is a plan view of a semiconductor element as seen from the surface thereof on which electrode pads are formed, FIG. 2(b) is a plan view of a semiconductor element-equipped surface of a board or substrate, and FIG. 2(c) is a plan view of an external electrode forming surface of the substrate. FIG. 3 is an enlarged view of a seal ring.
[0018] Referring to FIGS. 1 and 2, wires or interconnections [0018] 3 are formed over the surface of the substrate 1 made from an organic material by copper foil. An organic material, ceramic or the like is normally used as the material for the substrate. However, when the substrate is composed of the organic material, the copper foil is placed over the entire surface of the substrate 1 and thereafter subjected to etching, thereby forming interconnections 3 including pads 2 for connecting to the semiconductor element.
[0019] Upon etching at the formation of the interconnections [0019] 3, the copper foil is left even on the outer periphery of the substrate 1 as a seal ring 4 as shown in FIG. 3(a). The seal ring 4 is electrically connected to pads 6 a for forming external terminals electrically connected to ground via through holes 5 a defined in the substrate 1 and wires or interconnections 7 a formed on the back of the substrate 1. An epoxy resin filling material 11 may be charged into each through hole 5 a as shown in FIG. 3(b). Further, the seal ring 4 is electrically connected to its corresponding pads on the substrate, corresponding to electrodes connected to the ground of the semiconductor element through wires or interconnections 3 a on the surface of the substrate.
[0020] The interconnections [0020] 3 formed on the substrate are electrically connected to their corresponding pads 6 for forming external terminals, via through holes 5 and wires or interconnections 7 formed on the back of the substrate.
[0021] The frontal surface or front and back of the substrate [0021] 1 including the interconnections 3 and 7 are covered with a solder resist 8 in a state in which the pads 9 and 6 and the seal ring 4 are respectively bare.
[0022] A semiconductor element [0022] 12 is mounted over the surface of the substrate 1 with bump electrodes 10 interposed therebetween. Unillustrated circuit elements and electrode pads 13 respectively connected to the circuit elements are formed over the surface of the semiconductor element 12. The electrode pads 13 and the pads 2 provided on the surface of the substrate 1 are electrically connected to one another through the bump electrodes 10. Further, an epoxy resin 14 is charged between the surface of the semiconductor element 12 on which the bump electrodes 10 are formed and the substrate 1.
[0023] A metal-made cap [0023] 15 for covering the semiconductor element 12 is provided on the substrate 1. The cap 15 is electrically connected to the substrate 1 through the seal ring 4 and a conductive material 16 such as solder, an anisotropic conductive adhesive or the like both formed on the substrate 1. This connection may be performed by seam welding.
[0024] Upon formation of the cap [0024] 15, the cap 15 and the semiconductor element 12 are connected to each other by an insulating adhesive 17.
[0025] External terminals [0025] 18 such as solder balls or the like are formed on the pads 6 for forming the external terminals, which are formed over the back of the substrate. Here, the outermost-peripheral external terminals 18 a are electrically connected to the seal ring 4 provided on the surface of the substrate 1 through the through holes 5 a. When they are contained on the motherboard, they are electrically connected to wires or interconnections for supplying ground on the motherboard side.
[0026] According to the first embodiment as described above, the outermost-peripheral external terminals electrically connected to the metal-made cap are respectively electrically connected to the interconnections for respectively supplying ground on the motherboard side. As a result, the metal-made cap, which covers the semiconductor element and the upper surface of the substrate, is brought to a ground potential. Thus, the package will result in a structure in which it is electrically shielded from the outside. Therefore, since an electromagnetic wave produced from the inside upon activation of the device and an externally-incoming electromagnetic wave are shielded by the metal-made cap, the malfunction of a device due to the emission and entry of the electromagnetic waves can be reduced. [0026]
[0027] Further, the use of a high-heat conductive material as the insulative adhesive for connecting the semiconductor element to the metal-made cap can provide expectations for an improvement in dissipation of heat from a semiconductor chip (a reduction in thermal resistance as a package). [0027]
[0028] Further, a ceramic material may be used in place of the organic material as the material for the substrate. As an alternative to the interconnections formed by etching the copper foil in this case, the wires or interconnections are formed by printing conductive paste [0028] 19 such as copper, tungsten or the like as shown in FIG. 3(c) and thereafter the conductive paste 19 may be charged even into each through hole 5 a.
[0029] A second embodiment of the present invention will next be explained. [0029]
[0030] FIG. 4 is a cross-sectional view of a small-sized area array package showing the second embodiment of the present invention. Incidentally, the same elements of structure as those illustrated in the first embodiment are identified by the same reference numerals in FIG. 4 and their description will be omitted. [0030]
[0031] In the second embodiment, support pins (protrusions) [0031] 20 are provided at the four corners of the surfaces of a metal-made cap 15, which mate with a substrate 1. Further, the support pins 20 penetrate into through holes 21 defined in the corners of an outer peripheral seal ring 4 on the surface of the substrate 1 so that they are exposed from the back (corresponding to an external-terminal mounting surface) of the substrate 1. Thereafter, the support pins 20 bared from the substrate 1 upon mounting the motherboard are electrically connected to wires or interconnections for supplying ground on the motherboard side.
[0032] Incidentally, the length of each support pin [0032] 20 is set in such a manner that the portion of each support pin 20, which is exposed from the back of the substrate 1, becomes lower than the height of each external terminal 18 (the length of the support pin varies according to the diameter of the external terminal 18 to be used and the type of flux or the like). Even in this case, the same method as that in the first embodiment is used for joining together the substrate 1 and the metal-made cap 15 and joining together a semiconductor element 12 and the metal-made cap 15.
[0033] Thus, the emission of an electromagnetic wave and the penetration of an electromagnetic wave from the outside can be reduced by covering the small-sized area array package with the metal-made cap [0033] 15 and electrically connecting it to the ground on the motherboard side through the support pins 20 attached to the metal-made cap 15.
[0034] By setting the length of each support pin [0034] 20 protruded through the back of the substrate 1 so as to be lower than the height of each external terminal 18, the amount of sinking of the package due to the melting of each external terminal 18 upon mounting of the motherboard can be adjusted.
[0035] When the support pins attached to the metal-made cap are connected to the ground on the motherboard side where the package is configured in this way, the metal-made cap covering the semiconductor element and the upper surface of the substrate is brought to a ground potential. As a result, the package will result in a structure in which it is apparently electrically shielded from the outside. Therefore, since an electromagnetic wave produced from the inside upon activation of the device and an externally-incoming electromagnetic wave are shielded by the metal-made cap, the malfunction of the device due to the emission and entry of the electromagnetic waves can be reduced. [0035]
[0036] Further, since the metal-made cap is joined to the semiconductor chip through the high-heat conductive insulating adhesive, an improvement in dissipation of heat from the semiconductor chip (a reduction in thermal resistance as a package) can be achieved. [0036]
[0037] Setting the length of each support pin protruded through the back of the substrate so as to be lower than the height of each external terminal [0037] 18 allows an adjustment to the amount of sinking of the package due to the melting of each external terminal at the mounting of the motherboard. Thus, the package can be prevented from excessively sinking upon mounting of the motherboard, and flux cleanability after the mounting of the motherboard and the reliability of connection with the motherboard can be improved.
[0038] A third embodiment of the present invention will next be described with reference to FIG. 5 and FIGS. [0038] 6(a) through 6(c). Incidentally, the same elements of structure as those illustrated in the first embodiment are identified by the same reference numerals and their description will be omitted.
[0039] FIG. 5 is a cross-sectional view of the third embodiment. The third embodiment is different from the first embodiment in that it is formed by a multilayer board [0039] 30 provided therewithin with an intermediate layer 31 formed by a conductive layer.
[0040] FIG. 6([0040] a) is a plan view of the multilayer board 30 as viewed from the mounting side of a semiconductor element 12, FIG. 6(b) is a plan view showing the intermediate layer 31, and FIG. 6(c) is a plan view of the multilayer board 30 as seen from an external electrode forming surface, respectively.
[0041] The intermediate layer [0041] 31 composed of a metal material such as copper foil or tungsten or the like is provided in the multilayer board 30. The intermediate layer 31 is electrically connected to ground pads 32 of the semiconductor element 12 via through holes 34 and bump electrodes 33.
[0042] Further, the intermediate layer [0042] 31 is electrically connected via through holes 5 a to a seal ring 4 formed on the board and external terminals 18 a connected to ground.
[0043] External electrodes [0043] 18 supplied with signals such as an input and an output other than the ground are electrically connected to their corresponding electrodes of the semiconductor element via through holes 5. Spaces are provided around the through holes 5 disconnected to the ground so as to lie between the through holes 5 and the intermediate layer 31. They serve so as to prevent the through holes 5 and the intermediate layer 31 from contacting with each other.
[0044] Owing to the provision of the intermediate layer [0044] 31 as described above, the semiconductor element 12 is electrically cut off from the outside by a metal-made cap and the intermediate layer so that a higher shield effect can be expected.
[0045] When the external terminals [0045] 18 a connected to the ground are placed so as to be rendered uniform as viewed from the center of the multilayer board 30, the distribution of a current over the intermediate layer 31 provided within the multilayer board 30 becomes uniform as indicated by arrows in FIG. 7. Thus, an effect can be expected that the impedance of the ground within the package including the cap 15 connected to the ground external terminals 18 a is stabilized.
[0046] Further, when the external terminals placed on the outermost periphery of the multilayer board [0046] 30 are all set as the external terminals 18 a electrically connected to the ground, the distribution of a current over the intermediate layer 31 becomes more uniform and the outermost periphery of each external terminal 18 is placed in a state surrounded by the ground. Therefore, a shield effect including the external terminals can be expected.
[0047] In a manner similar to the case described in the second embodiment even in the case of the third embodiment, the cap may be provided with the support pins so as to extend through the through holes defined in the corners of the board. In this case, the amount of sinking of the package due to the melting of each external terminal at the mounting of the motherboard can be adjusted so that the package can be prevented from excessively sinking upon mounting of the motherboard. Further, flux cleanability after the mounting of the motherboard and the reliability of connection with the motherboard can be improved. [0047]
[0048] While the present invention has been described with reference to the illustrative embodiments, this description is not intended to be construed in a limiting sense. Various modifications of the illustrative embodiments, as well as other embodiments of the invention, will be apparent to those skilled in the art on reference to this description. It is therefore contemplated that the appended claims will cover any such modifications or embodiments as fall within the true scope of the invention. [0048]

权利要求:
Claims (17)
[1" id="US-20010008301-A1-CLM-00001] 1. A semiconductor device comprising:
a substrate having a surface with interconnection formed thereon;
a semiconductor element mounted on said substrate and electrically connected to the interconnections; and
a conductive cap for covering said semiconductor element electrically connected to a ground potential.
[2" id="US-20010008301-A1-CLM-00002] 2. The semiconductor device according to
claim 1 , wherein said interconnections formed on the surface of said substrate are connected to external electrodes formed on the back of said substrate via through holes extending through the front and back of said substrate.
[3" id="US-20010008301-A1-CLM-00003] 3. The semiconductor device according to
claim 1 , wherein said substrate has a conductive intermediate layer connected to the ground potential, which is provided between the front and back of said substrate.
[4" id="US-20010008301-A1-CLM-00004] 4. The semiconductor device according to
claim 1 or
2 , wherein said conductive cap protrudes through the back of said substrate via through holes defined in said substrate and has protrusions electrically connected to the ground potential.
[5" id="US-20010008301-A1-CLM-00005] 5. The semiconductor device according to
claim 4 , wherein said each protrusion is lower than the height of each external terminal.
[6" id="US-20010008301-A1-CLM-00006] 6. The semiconductor device according to
claim 1 , wherein said conductive cap is brought into contact with said semiconductor element through an insulating material.
[7" id="US-20010008301-A1-CLM-00007] 7. The semiconductor device according to
claim 2 , wherein said external electrodes connected to the ground potential, of said external electrodes are disposed substantially uniformly as viewed from the center of said substrate.
[8" id="US-20010008301-A1-CLM-00008] 8. The semiconductor device according to
claim 2 , wherein said external electrodes are formed in the form of a plurality of rows and said external terminals thereof located on the outermost periphery are brought to the ground potential.
[9" id="US-20010008301-A1-CLM-00009] 9. The semiconductor device according to
claim 4 , wherein said protrusions are disposed substantially uniformly as viewed from the center of said substrate.
[10" id="US-20010008301-A1-CLM-00010] 10. The semiconductor device according to
claim 4 , wherein said protrusions are provided around said substrate and said external terminals are respectively formed inside said protrusions.
[11" id="US-20010008301-A1-CLM-00011] 11. A semiconductor device comprising:
a substrate having a surface with interconnections and a conductive layer surrounding the periphery thereof both formed thereon;
a semiconductor element mounted on said substrate and electrically connected to said interconnections through electrodes formed on the surface of said substrate;
a conductive cap provided over the surface of said substrate so as to cover said semiconductor element and electrically connected to said conductive layer; and
external electrodes formed on the back of said substrate and electrically connected to said interconnections via through holes defined in said substrate.
[12" id="US-20010008301-A1-CLM-00012] 12. The semiconductor device according to
claim 11 , wherein said conductive layer is electrically connected to said external electrodes connected to a ground potential.
[13" id="US-20010008301-A1-CLM-00013] 13. The semiconductor device according to
claim 11 , wherein said substrate has a conductive intermediate layer lying between the front and back thereof and connected to the ground potential.
[14" id="US-20010008301-A1-CLM-00014] 14. The semiconductor device according to
claim 11 , wherein said semiconductor element is in contact with said conductive cap through an insulating material.
[15" id="US-20010008301-A1-CLM-00015] 15. A semiconductor device comprising:
a substrate having,
interconnections formed on the surface of said substrate;
a conductive layer formed around said surface;
a conductive intermediate layer formed between the front and back of said substrate;
a plurality of first through holes extending through the front and back thereof so as to connect to said conductive intermediate layer; and
a plurality of second through holes disconnected from said conductive intermediate layer;
a semiconductor element having a plurality of electrodes respectively connected to said interconnections, which include at least a plurality of signal electrodes for inputting or outputting signals and a plurality of ground electrodes connected to a ground potential;
a conductive cap connected to said conduction layer, for covering said semiconductor element;
a plurality of first external electrodes respectively connected to said ground electrodes through said plurality of first through holes; and
a plurality of second external electrodes respectively connected to said signal electrodes through said plurality of second through holes.
[16" id="US-20010008301-A1-CLM-00016] 16. The semiconductor device according to
claim 15 , wherein said plurality of first external electrodes are placed substantially uniformly as viewed from the center of said substrate.
[17" id="US-20010008301-A1-CLM-00017] 17. The semiconductor device according to
claim 15 , wherein said plurality of first external electrodes are disposed in the neighborhood of ends of said substrate so as to surround other external electrodes.

类似技术:

公开号 | 公开日 | 专利标题

US6225694B1|2001-05-01|Semiconductor device

US7161242B2|2007-01-09|Semiconductor device, semiconductor device substrate, and manufacturing method thereof that can increase reliability in mounting a semiconductor element

US6084295A|2000-07-04|Semiconductor device and circuit board used therein

JP2780649B2|1998-07-30|Semiconductor device

US6534879B2|2003-03-18|Semiconductor chip and semiconductor device having the chip

US6734557B2|2004-05-11|Semiconductor device

US5309021A|1994-05-03|Semiconductor device having particular power distribution interconnection arrangement

JPH09260552A|1997-10-03|Mounting structure of semiconductor chip

US6111761A|2000-08-29|Electronic assembly

JP3228339B2|2001-11-12|Semiconductor device and method of manufacturing the same

KR20000011282A|2000-02-25|Semiconductor device and manufacturing method thereof

US6037656A|2000-03-14|Semiconductor integrated circuit device having short signal paths to terminals and process of fabrication thereof

JP2004214460A|2004-07-29|Semiconductor device

TW541632B|2003-07-11|Semiconductor device and manufacturing method thereof, circuit board and electronic equipment

US20020140110A1|2002-10-03|Semiconductor chip mounting substrate and semiconductor device using the same

JP2803656B2|1998-09-24|Semiconductor device

JP2003218472A|2003-07-31|Module and surface-mounted module

JP3715120B2|2005-11-09|Hybrid module

US6472759B1|2002-10-29|Ball grid array type semiconductor device

US6020631A|2000-02-01|Method and apparatus for connecting a bondwire to a bondring near a via

JP3033662B2|2000-04-17|Semiconductor element mounting film and semiconductor element mounting structure

US6278190B1|2001-08-21|Semiconductor device

US6291893B1|2001-09-18|Power semiconductor device for “flip-chip” connections

JP3090115B2|2000-09-18|Semiconductor device and manufacturing method thereof

JP3065288B2|2000-07-17|Semiconductor bare chip sealing method, semiconductor integrated circuit device, and method of manufacturing semiconductor integrated circuit device

同族专利:

公开号 | 公开日

KR19990029419A|1999-04-26|

JP3834426B2|2006-10-18|

US6538319B2|2003-03-25|

JPH11145333A|1999-05-28|

KR100404159B1|2004-02-05|

US6225694B1|2001-05-01|

引用文献:

公开号 | 申请日 | 公开日 | 申请人 | 专利标题

US20030015772A1|2001-07-23|2003-01-23|Ivanov Tony G.|Method and structure for DC and RF shielding of integrated circuits|

US20050248418A1|2003-03-28|2005-11-10|Vinu Govind|Multi-band RF transceiver with passive reuse in organic substrates|

US20060185893A1|2005-02-22|2006-08-24|Alps Electric Co., Ltd.|Surface-mounting type electronic circuit unit without detachment of solder|

US20070262427A1|2005-01-25|2007-11-15|Fujitsu Limited|Semiconductor device|

US20070273035A1|1998-12-21|2007-11-29|Mou-Shiung Lin|Top layers of metal for high performance IC's|

US20080272468A1|2007-05-02|2008-11-06|Farshad Ghaghahi|Grounded shield for blocking electromagnetic interference in an integrated circuit package|

US20090001548A1|2007-06-27|2009-01-01|Elpida Memory, Inc.|Semiconductor package|

US20090278219A1|2008-05-07|2009-11-12|Micron Technology, Inc.|Microelectronic devices having an emi shield and associated systems and methods|

US20100308451A1|2009-06-03|2010-12-09|Shinko Electric Industries Co., Ltd.|Wiring substrate and method of manufacturing the same|

US20110127654A1|2009-11-27|2011-06-02|Advanced Semiconductor Engineering, Inc..,|Semiconductor Package and Manufacturing Methods Thereof|

US20120074559A1|2010-09-24|2012-03-29|International Business Machines Corporation|Integrated circuit package using through substrate vias to ground lid|

CN102623438A|2011-01-31|2012-08-01|株式会社东芝|Semiconductor device|

CN102714195A|2009-12-14|2012-10-03|松下电器产业株式会社|Semiconductor device|

CN103219295A|2012-01-20|2013-07-24|环旭电子股份有限公司|Conformal mask packaging structure and detection method|

CN103907404A|2011-11-04|2014-07-02|苹果公司|Electromagnetic interference shielding techniques|

US8874048B2|2012-02-28|2014-10-28|Kabushiki Kaisha Toshiba|Wireless device, and information processing apparatus and storage device including the wireless device|

US8884424B2|2010-01-13|2014-11-11|Advanced Semiconductor Engineering, Inc.|Semiconductor package with single sided substrate design and manufacturing methods thereof|

US8941222B2|2010-11-11|2015-01-27|Advanced Semiconductor Engineering Inc.|Wafer level semiconductor package and manufacturing methods thereof|

US9166298B2|2012-08-24|2015-10-20|Kabushiki Kaisha Toshiba|Wireless device, and information processing apparatus and storage device including the wireless device|

US9349611B2|2010-03-22|2016-05-24|Advanced Semiconductor Engineering, Inc.|Stackable semiconductor package and manufacturing method thereof|

US9406658B2|2010-12-17|2016-08-02|Advanced Semiconductor Engineering, Inc.|Embedded component device and manufacturing methods thereof|

EP3882967A3|2020-03-19|2021-09-29|Intel Corporation|Memory device package with noise shielding|US4410905A|1981-08-14|1983-10-18|Amp Incorporated|Power, ground and decoupling structure for chip carriers|

US5490324A|1993-09-15|1996-02-13|Lsi Logic Corporation|Method of making integrated circuit package having multiple bonding tiers|

GB2288286A|1994-03-30|1995-10-11|Plessey Semiconductors Ltd|Ball grid array arrangement|

US5741729A|1994-07-11|1998-04-21|Sun Microsystems, Inc.|Ball grid array package for an integrated circuit|

JP2780649B2|1994-09-30|1998-07-30|日本電気株式会社|Semiconductor device|

US5572070A|1995-02-06|1996-11-05|Rjr Polymers, Inc.|Integrated circuit packages with heat dissipation for high current load|

US5789810A|1995-12-21|1998-08-04|International Business Machines Corporation|Semiconductor cap|

US5898219A|1997-04-02|1999-04-27|Intel Corporation|Custom corner attach heat sink design for a plastic ball grid array integrated circuit package|US6117797A|1998-09-03|2000-09-12|Micron Technology, Inc.|Attachment method for heat sinks and devices involving removal of misplaced encapsulant|

US6711812B1|1999-04-13|2004-03-30|Unicap Electronics Industrial Corporation|Method of making metal core substrate printed circuit wiring board enabling thermally enhanced ball grid arraypackages|

JP2001053178A|1999-06-02|2001-02-23|Japan Radio Co Ltd|Electronic component with electronic circuit device sealed and mounted on circuit board, and manufacture of the electronic component|

JP2001127211A|1999-10-26|2001-05-11|Nec Corp|Semiconductor integrated circuit provided with electromagnetic wave noise shielding part and packaging structure for the semiconductor integrated circuit|

JP3467454B2|2000-06-05|2003-11-17|Ｎｅｃエレクトロニクス株式会社|Method for manufacturing semiconductor device|

JP3407025B2|2000-06-08|2003-05-19|Ｎｅｃエレクトロニクス株式会社|Semiconductor device and manufacturing method thereof|

KR100600169B1|2000-07-18|2006-07-12|앰코 테크놀로지 코리아 주식회사|Semiconductor package|

GB2365007B|2000-07-21|2002-06-26|Murata Manufacturing Co|Insulative ceramic compact|

KR100645755B1|2000-11-07|2006-11-13|앰코 테크놀로지 코리아 주식회사|Semiconductor package and method for manufacturing the same|

US6518678B2|2000-12-29|2003-02-11|Micron Technology, Inc.|Apparatus and method for reducing interposer compression during molding process|

KR100411206B1|2001-02-19|2003-12-18|삼성전자주식회사|Semiconductor package|

US6856007B2|2001-08-28|2005-02-15|Tessera, Inc.|High-frequency chip packages|

DE10142971A1|2001-09-01|2003-03-27|Eupec Gmbh & Co Kg|The power semiconductor module|

DE10148120B4|2001-09-28|2007-02-01|Infineon Technologies Ag|Electronic components with semiconductor chips and a system carrier with component positions and method for producing a system carrier|

US6800944B2|2001-12-19|2004-10-05|Texas Instruments Incorporated|Power/ground ring substrate for integrated circuits|

US7535093B1|2002-03-08|2009-05-19|Raytheon Company|Method and apparatus for packaging circuit devices|

US7026223B2|2002-03-28|2006-04-11|M/A-Com, Inc|Hermetic electric component package|

JP3923368B2|2002-05-22|2007-05-30|シャープ株式会社|Manufacturing method of semiconductor device|

US6977187B2|2002-06-19|2005-12-20|Foster-Miller, Inc.|Chip package sealing method|

US6972481B2|2002-09-17|2005-12-06|Chippac, Inc.|Semiconductor multi-package module including stacked-die package and having wire bond interconnect between stacked packages|

US7053476B2|2002-09-17|2006-05-30|Chippac, Inc.|Semiconductor multi-package module having package stacked over die-down flip chip ball grid array package and having wire bond interconnect between stacked packages|

US7064426B2|2002-09-17|2006-06-20|Chippac, Inc.|Semiconductor multi-package module having wire bond interconnect between stacked packages|

US7205647B2|2002-09-17|2007-04-17|Chippac, Inc.|Semiconductor multi-package module having package stacked over ball grid array package and having wire bond interconnect between stacked packages|

US20040061213A1|2002-09-17|2004-04-01|Chippac, Inc.|Semiconductor multi-package module having package stacked over die-up flip chip ball grid array package and having wire bond interconnect between stacked packages|

US6838761B2|2002-09-17|2005-01-04|Chippac, Inc.|Semiconductor multi-package module having wire bond interconnect between stacked packages and having electrical shield|

US7049691B2|2002-10-08|2006-05-23|Chippac, Inc.|Semiconductor multi-package module having inverted second package and including additional die or stacked package on second package|

CA2409912C|2002-10-25|2008-04-01|Ibm Canada Limited-Ibm Canada Limitee|Improvements in grounding and thermal dissipation for integrated circuit packages|

JP3908148B2|2002-10-28|2007-04-25|シャープ株式会社|Multilayer semiconductor device|

US20040150097A1|2003-01-30|2004-08-05|International Business Machines Corporation|Optimized conductive lid mounting for integrated circuit chip carriers|

US7754537B2|2003-02-25|2010-07-13|Tessera, Inc.|Manufacture of mountable capped chips|

US7034387B2|2003-04-04|2006-04-25|Chippac, Inc.|Semiconductor multipackage module including processor and memory package assemblies|

US6747350B1|2003-06-06|2004-06-08|Silicon Integrated Systems Corp.|Flip chip package structure|

JP2007528120A|2003-07-03|2007-10-04|テッセラテクノロジーズハンガリーコルラートルトフェレロェセーギュータールシャシャーグ|Method and apparatus for packaging integrated circuit devices|

US7144640B2|2003-08-01|2006-12-05|Agency For Science, Technology And Research|Tilted media for hard disk drives and magnetic data storage devices|

US7012326B1|2003-08-25|2006-03-14|Xilinx, Inc.|Lid and method of employing a lid on an integrated circuit|

US20050095835A1|2003-09-26|2005-05-05|Tessera, Inc.|Structure and method of making capped chips having vertical interconnects|

US6982481B1|2003-10-08|2006-01-03|Nortel Networks Limited|System for dissipating heat and shielding electromagnetic radiation produced by an electronic device|

WO2005059967A2|2003-12-17|2005-06-30|Chippac, Inc.|Multiple chip package module having inverted package stacked over die|

DE102004012818B3|2004-03-16|2005-10-27|Infineon Technologies Ag|Method for producing a power semiconductor component|

US20050258527A1|2004-05-24|2005-11-24|Chippac, Inc.|Adhesive/spacer island structure for multiple die package|

US20050269692A1|2004-05-24|2005-12-08|Chippac, Inc|Stacked semiconductor package having adhesive/spacer structure and insulation|

US8552551B2|2004-05-24|2013-10-08|Chippac, Inc.|Adhesive/spacer island structure for stacking over wire bonded die|

US7253511B2|2004-07-13|2007-08-07|Chippac, Inc.|Semiconductor multipackage module including die and inverted land grid array package stacked over ball grid array package|

DE102004036909B4|2004-07-29|2007-04-05|Infineon Technologies Ag|A semiconductor base device with a wiring substrate and an intermediate wiring board for a semiconductor device stack, and a method of manufacturing the same|

US8143095B2|2005-03-22|2012-03-27|Tessera, Inc.|Sequential fabrication of vertical conductive interconnects in capped chips|

US7364945B2|2005-03-31|2008-04-29|Stats Chippac Ltd.|Method of mounting an integrated circuit package in an encapsulant cavity|

KR101213661B1|2005-03-31|2012-12-17|스태츠 칩팩, 엘티디.|Semiconductor assembly including chip scale package and second substrate and having exposed substrate surfaces on upper and lower sides|

US7429786B2|2005-04-29|2008-09-30|Stats Chippac Ltd.|Semiconductor package including second substrate and having exposed substrate surfaces on upper and lower sides|

US7354800B2|2005-04-29|2008-04-08|Stats Chippac Ltd.|Method of fabricating a stacked integrated circuit package system|

US7582960B2|2005-05-05|2009-09-01|Stats Chippac Ltd.|Multiple chip package module including die stacked over encapsulated package|

US7394148B2|2005-06-20|2008-07-01|Stats Chippac Ltd.|Module having stacked chip scale semiconductor packages|

US7388284B1|2005-10-14|2008-06-17|Xilinx, Inc.|Integrated circuit package and method of attaching a lid to a substrate of an integrated circuit|

JP4860994B2|2005-12-06|2012-01-25|ルネサスエレクトロニクス株式会社|Semiconductor device|

US7646092B2|2005-12-06|2010-01-12|Yamaha Corporation|Semiconductor device and manufacturing method thereof|

US7768125B2|2006-01-04|2010-08-03|Stats Chippac Ltd.|Multi-chip package system|

US7456088B2|2006-01-04|2008-11-25|Stats Chippac Ltd.|Integrated circuit package system including stacked die|

US7936062B2|2006-01-23|2011-05-03|Tessera Technologies Ireland Limited|Wafer level chip packaging|

US7750482B2|2006-02-09|2010-07-06|Stats Chippac Ltd.|Integrated circuit package system including zero fillet resin|

JP4703424B2|2006-02-10|2011-06-15|大日本印刷株式会社|Compound sensor package|

US8704349B2|2006-02-14|2014-04-22|Stats Chippac Ltd.|Integrated circuit package system with exposed interconnects|

JP2007227778A|2006-02-24|2007-09-06|Alps Electric Co Ltd|Surface-mounting electronic circuit module|

US20080029879A1|2006-03-01|2008-02-07|Tessera, Inc.|Structure and method of making lidded chips|

US20080128890A1|2006-11-30|2008-06-05|Advanced Semiconductor Engineering, Inc.|Chip package and fabricating process thereof|

US8604605B2|2007-01-05|2013-12-10|Invensas Corp.|Microelectronic assembly with multi-layer support structure|

JP2010519769A|2007-02-21|2010-06-03|ラムバス・インコーポレーテッド|High speed memory package|

US20080266806A1|2007-04-27|2008-10-30|Lakin Eric D|Electronic assembly that includes a heat sink which cools multiple electronic components|

US20080266807A1|2007-04-27|2008-10-30|Cray Inc.|Electronic assembly with emi shielding heat sink|

JP2009117767A|2007-11-09|2009-05-28|Shinko Electric Ind Co Ltd|Manufacturing method of semiconductor device, and semiconductor device manufacture by same|

US7989928B2|2008-02-05|2011-08-02|Advanced Semiconductor Engineering Inc.|Semiconductor device packages with electromagnetic interference shielding|

US8022511B2|2008-02-05|2011-09-20|Advanced Semiconductor Engineering, Inc.|Semiconductor device packages with electromagnetic interference shielding|

US8350367B2|2008-02-05|2013-01-08|Advanced Semiconductor Engineering, Inc.|Semiconductor device packages with electromagnetic interference shielding|

US8212339B2|2008-02-05|2012-07-03|Advanced Semiconductor Engineering, Inc.|Semiconductor device packages with electromagnetic interference shielding|

US7906857B1|2008-03-13|2011-03-15|Xilinx, Inc.|Molded integrated circuit package and method of forming a molded integrated circuit package|

US7906376B2|2008-06-30|2011-03-15|Intel Corporation|Magnetic particle-based composite materials for semiconductor packages|

JP5277755B2|2008-07-01|2013-08-28|オムロン株式会社|Electronic components|

US8410584B2|2008-08-08|2013-04-02|Advanced Semiconductor Engineering, Inc.|Semiconductor device packages with electromagnetic interference shielding|

US20100110656A1|2008-10-31|2010-05-06|Advanced Semiconductor Engineering, Inc.|Chip package and manufacturing method thereof|

JP5169800B2|2008-12-22|2013-03-27|株式会社デンソー|Electronic equipment|

WO2010087856A1|2009-01-30|2010-08-05|Hewlett-Packard Development Company, L.P.|Integrated-circuit attachment structure with solder balls and pins|

US20100207257A1|2009-02-17|2010-08-19|Advanced Semiconductor Engineering, Inc.|Semiconductor package and manufacturing method thereof|

US8110902B2|2009-02-19|2012-02-07|Advanced Semiconductor Engineering, Inc.|Chip package and manufacturing method thereof|

US8916958B2|2009-04-24|2014-12-23|Infineon Technologies Ag|Semiconductor package with multiple chips and substrate in metal cap|

US20110001230A1|2009-07-02|2011-01-06|Conexant Systems, Inc.|Systems and Methods of Improved Heat Dissipation with Variable Pitch Grid Array Packaging|

US8212340B2|2009-07-13|2012-07-03|Advanced Semiconductor Engineering, Inc.|Chip package and manufacturing method thereof|

US8362609B1|2009-10-27|2013-01-29|Xilinx, Inc.|Integrated circuit package and method of forming an integrated circuit package|

US8368185B2|2009-11-19|2013-02-05|Advanced Semiconductor Engineering, Inc.|Semiconductor device packages with electromagnetic interference shielding|

US8030750B2|2009-11-19|2011-10-04|Advanced Semiconductor Engineering, Inc.|Semiconductor device packages with electromagnetic interference shielding|

US8378466B2|2009-11-19|2013-02-19|Advanced Semiconductor Engineering, Inc.|Wafer-level semiconductor device packages with electromagnetic interference shielding|

US9254532B2|2009-12-30|2016-02-09|Intel Corporation|Methods of fabricating low melting point solder reinforced sealant and structures formed thereby|

EP2549534B1|2010-03-16|2019-07-03|Fuji Electric Co., Ltd.|Semiconductor device|

CA2704683A1|2010-05-28|2010-08-12|Ibm Canada Limited - Ibm Canada Limitee|Grounded lid for micro-electronic assemblies|

JP5572890B2|2010-06-08|2014-08-20|ミヨシ電子株式会社|Semiconductor module and semiconductor device|

JP2011258757A|2010-06-09|2011-12-22|Toshiba Corp|Semiconductor device|

US8810028B1|2010-06-30|2014-08-19|Xilinx, Inc.|Integrated circuit packaging devices and methods|

US9007273B2|2010-09-09|2015-04-14|Advances Semiconductor Engineering, Inc.|Semiconductor package integrated with conformal shield and antenna|

KR20120045893A|2010-11-01|2012-05-09|삼성전기주식회사|Semiconductor package module|

KR101708093B1|2011-03-22|2017-02-17|르네사스 일렉트로닉스 가부시키가이샤|Semiconductor device|

US8748233B2|2011-06-21|2014-06-10|Stats Chippac Ltd.|Integrated circuit packaging system with underfill and method of manufacture thereof|

FR2977975A1|2011-07-13|2013-01-18|St Microelectronics Grenoble 2|THERMAL VIA ELECTRONIC HOUSING AND METHOD OF MANUFACTURE|

KR101829392B1|2011-08-23|2018-02-20|삼성전자주식회사|Semiconductor package and method of forming the same|

US8541883B2|2011-11-29|2013-09-24|Advanced Semiconductor Engineering, Inc.|Semiconductor device having shielded conductive vias|

US8937376B2|2012-04-16|2015-01-20|Advanced Semiconductor Engineering, Inc.|Semiconductor packages with heat dissipation structures and related methods|

US8786060B2|2012-05-04|2014-07-22|Advanced Semiconductor Engineering, Inc.|Semiconductor package integrated with conformal shield and antenna|

US8704341B2|2012-05-15|2014-04-22|Advanced Semiconductor Engineering, Inc.|Semiconductor packages with thermal dissipation structures and EMI shielding|

US8653634B2|2012-06-11|2014-02-18|Advanced Semiconductor Engineering, Inc.|EMI-shielded semiconductor devices and methods of making|

US9153542B2|2012-08-01|2015-10-06|Advanced Semiconductor Engineering, Inc.|Semiconductor package having an antenna and manufacturing method thereof|

US9978688B2|2013-02-28|2018-05-22|Advanced Semiconductor Engineering, Inc.|Semiconductor package having a waveguide antenna and manufacturing method thereof|

US9837701B2|2013-03-04|2017-12-05|Advanced Semiconductor Engineering, Inc.|Semiconductor package including antenna substrate and manufacturing method thereof|

US9129954B2|2013-03-07|2015-09-08|Advanced Semiconductor Engineering, Inc.|Semiconductor package including antenna layer and manufacturing method thereof|

US9172131B2|2013-03-15|2015-10-27|Advanced Semiconductor Engineering, Inc.|Semiconductor structure having aperture antenna|

CN103400825B|2013-07-31|2016-05-18|日月光半导体制造股份有限公司|Semiconductor package part and manufacture method thereof|

JP6157998B2|2013-09-03|2017-07-05|ルネサスエレクトロニクス株式会社|Semiconductor device|

US8912641B1|2013-09-09|2014-12-16|Harris Corporation|Low profile electronic package and associated methods|

US9232686B2|2014-03-27|2016-01-05|Intel Corporation|Thin film based electromagnetic interference shielding with BBUL/coreless packages|

KR102210332B1|2014-09-05|2021-02-01|삼성전자주식회사|Semiconductor package|

JP6720187B2|2014-09-16|2020-07-08|アンフェノール・エフシーアイ・アジア・ピーティーイー．・リミテッドＡｍｐｈｅｎｏｌＦＣＩＡｓｉａＰｔｅ．Ｌｔｄ．|Hermetically sealed electrical connector assembly|

US9666539B1|2015-12-03|2017-05-30|International Business Machines Corporation|Packaging for high speed chip to chip communication|

WO2019092938A1|2017-11-13|2019-05-16|オリンパス株式会社|Semiconductor substrate, semiconductor substrate laminate, and endoscope|

法律状态:
2003-03-06| STCF| Information on status: patent grant|Free format text: PATENTED CASE |

2006-09-01| FPAY| Fee payment|Year of fee payment: 4 |

2009-02-19| AS| Assignment|Owner name: OKI SEMICONDUCTOR CO., LTD., JAPAN Free format text: CHANGE OF NAME;ASSIGNOR:OKI ELECTRIC INDUSTRY CO., LTD.;REEL/FRAME:022299/0368 Effective date: 20081001 Owner name: OKI SEMICONDUCTOR CO., LTD.,JAPAN Free format text: CHANGE OF NAME;ASSIGNOR:OKI ELECTRIC INDUSTRY CO., LTD.;REEL/FRAME:022299/0368 Effective date: 20081001 |

2010-08-26| FPAY| Fee payment|Year of fee payment: 8 |

2014-03-21| AS| Assignment|Owner name: LAPIS SEMICONDUCTOR CO., LTD., JAPAN Free format text: CHANGE OF NAME;ASSIGNOR:OKI SEMICONDUCTOR CO., LTD;REEL/FRAME:032495/0483 Effective date: 20111003 |

2014-08-27| FPAY| Fee payment|Year of fee payment: 12 |

2014-12-16| AS| Assignment|Owner name: HPLP TECHNOLOGIES INC., CALIFORNIA Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:LAPIS SEMICONDUCTOR CO., LTD;REEL/FRAME:034513/0807 Effective date: 20141020 |

优先权:

申请号 | 申请日 | 专利标题

JP236854/97||1997-09-02||

JP23685497||1997-09-02||

JP9-236854||1997-09-02||

JP10-170071||1998-06-17||

JP17007198A|JP3834426B2|1997-09-02|1998-06-17|Semiconductor device|

US09/141,751|US6225694B1|1997-09-02|1998-08-28|Semiconductor device|

US09/777,676|US6538319B2|1997-09-02|2001-02-07|Semiconductor device|US09/777,676| US6538319B2|1997-09-02|2001-02-07|Semiconductor device|

[返回顶部]